1. Field of the Invention
The present invention generally relates to a semiconductor device, in particular, to an electronic circuit of fin field effect transistor (FET) and method for fabricating the electronic circuit of fin FET.
2. Description of Related Art
As the request to reduce the size of electronic device and increase the operation speed of electronic device, the size of the semiconductor device such as FET needs to be accordingly reduced. When size of the FET is greatly reduced, the conventional FET with polysilicon gate cannot be adapted well. So, the structure of FET in 2D structure is no longer suitable for use.
In the technologies under development, a type of fin FET has been proposed. The fin FET is in 3D structure, in which the source/drain region has been raised up from the substrate, like a fin in structure. The gate can be fondled as a gate line, crossing over the fin to serve as the gate structure for each FET and also the connection part between the related FET.
An electronic circuit is usually made from multiple fin FETs, which in view of locations can be treated as a fin FET array. In the conventional fin FET array, the polysilicon lines, as the gate lines, have the same line width without concerning the unbalance stress due to the poly slot (discontinuous part), which is deposited with oxide later.
It has been found and investigated in the invention that at least an issue of circuit short for the gate line may occur when the later conductive structure is formed over the slot. Further improvement to the fin FET is still undergoing in the art.